OR1200: bug in Altera Implementation
When trying to implement the OpenRISC 1200 on an Altera Stratix FPGA, I discovered that there was a problem in the registers of the CPU. Damjan Lampret pointed to me that Xilinx Dual Port RAMs aren't the same as Altera Dual Port RAMs. (one uses registered RAM outputs and the other uses sampled
control signals IIRC)
So, when implementing OR1200 on Altera Stratix or Cyclone devices, don't use OR1200_RFRAM_DUALPORT (OR1200_defines.v). Instead use OR1200_RFRAM_GENERIC.